1. The Field of the Invention
The present invention may relate to phase-locked loop systems.
2. The Relevant Technology
A phase-locked loop system is a control system configured to generate a source signal having a fixed phase relationship to a reference signal. Phase-locked loops are widely used in radio, telecommunications, computers, and other electronic applications. Phase-locked loops may be used in a number of applications, including clock and data recovery (CDR) circuits. For example, in some systems, data may be transmitted to a receiver without additional timing reference and the timing information may be recovered at the receiver using a CDR circuit.
FIG. 1 illustrates an example of a conventional analog phase-locked loop 100. The phase-locked loop 100 may input a reference signal 102 and output a source signal 104. The phase of the output source signal 104 may be related to the phase of the reference signal 102.
The phase-locked loop 100 may include a phase detector 106. The phase detector 106 may receive as an input the reference signal 102 and the source signal 104 and produce a correction signal 110 indicating the phase difference of the reference signal 102 and the source signal 104. A number of phase detector designs may be available for generating a correction signal 110. Phase detectors are usually characterized as linear and nonlinear. A linear phase detector has output signal that is proportional to the difference in the phase relationship between the reference signal 102 and the source signal 104. A nonlinear phase detector has no such proportionality and usually has two states: early or late. A nonlinear phase detector is also known as a digital phase detector. The correction signal 110 may be filtered by a loop filter 112 to generate a control signal 114. The loop filter 112 may include a low-pass filter to attenuate high-frequency portions of the correction signal 110. This low-pass filter is commonly implemented in the form of an integrator with a compensating zero. The integrator with a compensating zero is usually implemented with a charge pump circuit and a series resistor-capacitor. The required capacitance is typically very large (much greater than 1 nF) so it is usually an external component, making it difficult to introduce the integrator with a compensating zero into integrated circuit (IC) technologies.
The phase-locked loop 100 may include a voltage-controlled oscillator 116. The voltage-controlled oscillator 116 may generally be configured to output an oscillating signal, for example, the source signal 104. The frequency of the oscillating signal may be dependent on the voltage input by the voltage-controlled oscillator 116. The control signal 114 may drive a voltage-controlled oscillator 116 to generate the source signal 104 with a periodic oscillation. The frequency of the source signal 104 may be controlled by the voltage of the control signal 114.
If the source signal 104 and the reference signal 102 are phase matched, the voltage of the control signal 114, and thus, the frequency of the source signal 104 may remain unchanged. If the phase of the source signal 104 falls behind the phase of the reference signal 102, the phase detector 106 may generate a correction signal 110 such that a resulting control signal 114 causes the voltage-controlled oscillator 116 to speed up the frequency of the source signal 104. For example, the voltage of the control signal 114 may increase. Conversely, if the phase of the source signal 104 moves ahead of the reference signal 102, the phase detector 106 may generate the correction signal 110 such that the control signal 114 causes the voltage-controlled oscillator 116 to slow down the frequency of the source signal 104. For example, the voltage of the control signal 114 may decrease.
In some systems, the source signal 104 and the reference signal 102 may lose the ability to phase lock if the reference frequency is too high or too low. For example, the source signal 104 and the reference signal 102 may lose the ability to phase lock if the voltage required to produce a frequency match is unattainable by the system. In some systems, if the phase-locked loop 100 is unable to achieve a lock, the voltage of the control signal 114 may be driven near a supply voltage or a ground voltage of the system. In some systems, a window comparator may monitor the voltage of the control signal 114 during the frequency acquiring phase of the loop. If the final-converged voltage of the control signal 114 is below a high threshold and above a low threshold, the window comparator may output a signal indicating that the source signal 104 is locked in frequency to the reference signal 102 in a proper range as to guarantee lock over all environmental conditions for which the CDR was designed. The high threshold may be based on the supply voltage and the low threshold may be based on the ground voltage. If the voltage of the control signal 114 is above the high threshold or below the low threshold, the window comparator may output a signal indicating that the source signal 104 is not locked in frequency to the reference signal 102.
In some applications, the source signal 104 may be used to determine a timing reference (clock) of a reference signal 102. For example, in some communication systems, data may be transmitted to a receiver without additional clock information. For example, in some optical communication systems, data may be transmitted over optical fibers to be received at receivers without accompanying clock information. In some embodiments, the phase-locked loop 100 may be used to derive clock information from the received data, commonly known as CDR.
The conventional CDR also requires a loop filter as shown in FIG. 1. It will also require large capacitance such that it would be very difficult to integrate that component in modern IC technologies.
FIG. 2 illustrates a conventional digital phase-locked loop 200 including a digital filter 206. The correction signal 110 is converted to a digital correction signal 202 by the analog-to-digital converter 204. The digital correction signal 202 may be processed by the digital filter 206 using digital signal processing techniques to obtain the equivalent filtering of the loop filter 112 as described with reference to FIG. 1. The digital filter output 208 may be converted to an analog signal 210 by a digital-to-analog converter 212. Alternately, the digital filter output 208 may drive a digitally-controlled oscillator (not shown) directly.
The embodiments described in this document describe systems and methods of digitizing the output of a digital phase detector that result in very low power and compact size suitable for high level of integration using modern IC technologies.
The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one exemplary technology area where some embodiments described herein may be practiced.